A vertical transistor used in the field of power electronics typically consists of a plurality of single transistor cells arranged in a parallel manner and a terminal contact for the gate electrode, as is for instance described in U.S. Pat. No. 5,844,277, cf. FIGS. 2A to D and FIGS. 5-7, and U.S. Pat. No. 5,763,914. These single transistor cells have a common gate electrode, a common drain terminal at the back side of the silicon wafer and separate source or well terminals within the silicon that, however, are connected in parallel by a common metal electrode. The number and the size of the single transistor cells determine the transistor area, the channel width and the on-resistance, as is described by Baliga in Power Semiconductor Devices, 1995, pages 367 onwards. In order to obtain the desired on-resistance of a vertical DMOS transistor in conventional techniques the entire transistor including a corresponding active area and an edge structure connectable to the periphery has to designed. Starting from a transistor having a first on-resistance to obtain a second transistor having a differing on-resistance it is necessary to newly design the entire transistor. Typically, the required electric parameters of the vertical DMOS transistor are measured and described separately for each different transistor.
For designing integrated circuits methods are known in which the circuit is composed by individual blocks. As e.g. shown in U.S. Pat. No. 6,769,007, in which is described the composing of an integrated circuit on the basis of individual blocks. Also, the composing of an integrated circuit or parts thereof on the basis of individual blocks separately to be connected by metal conductors is described in U.S. Pat. No. 6,651,236 and U.S. Pat. No. 6,591,408.